Contents
Preface xiii
Foreword xv
Acknowledgments xix
Chapter 1: Libraries 1
1.1 Standard Cells 2
1.2 Transistor Sizing 12
1.3 Input-Output Pads 16
1.4 Library Characterization 25
1.5 Summary 34
Chapter 2: Floorplanning 37
2.1 Technology File 38
2.2 Circuit Description 40
2.3 Design Constraints 45
2.4 Design Planning 47
2.5 Pad Placement 51
2.6 Power Planning 54
2.7 Macro Placement 58
2.8 Clock Planning 64
2.9 Summary 66
Chapter 3: Placement 71
3.1 Global Placement 72
3.2 Detail Placement 81
3.3 Clock Tree Synthesis 89
3.4 Power Analysis 99
3.5 Summary 102
Chapter 4: Routing 105
4.1 Special Routing 106
4.2 Global Routing 108
4.3 Detail Routing 115
4.4 Extraction 123
4.5 Summary 141
Chapter 5: Verification 145
5.1 Functional Verification 146
5.2 Timing Verification 149
5.3 Physical Verification 171
5.4 Summary 175
Chapter 6: Testing 179
6.1 Functional Test 181
6.2 Scan Test 185
6.3 Boundary Scan Test 188
6.4 Fault Detection 190
6.5 Parametric Test 192
6.6 Current and Very Low-level Voltage Test 194
6.7 Wafer Acceptance Test 196
6.8 Memory Test 199
x Contents
xi
6.10 Summary
202
Index 205
PHYSICAL DESIGN ESSENTIALS-An ASIC Design Implementation Perspective: 1.jpg
