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In 1980, I was designing my first three chips at Bell Labs for the No. 5 Electronic
Switching System (5ESS). These chips included a NMOS standard cell device
and two bipolar gate arrays. The NMOS chip took me three months to design,
and another three months to write test vectors that barely achieved 95% single stuckat
gate-level fault coverage. I decided that there had to be a better way to test these
devices than the monotony of manually performing path sensitization day after day to
determine what vectors I needed to detect a handful of faults. Even worse was running
fault simulations only to see a miserably small increase in fault coverage.
That year, I attended the IEEE International Test Conference (ITC) for the first time
and learned a great deal about design for testability. But the one thing I remember the
most was a presentation by Richard Sedmak on Built-In Self-Test which received the
best paper award for that year (actually the term BIST was not yet in use and Rich
referred to it as “self-verification”). While listening to his talk about designing chips
that could test themselves, I thought to myself, “This is crazy! It will never work! You
can’t tell if the chip is lying to you or not!” Then I thought, “Wait a minute - if I think
that the chip can lie and say that it is good when it is really faulty, then I must believe
that it can be designed to test itself. The real challenge has to be figuring out a way to
make sure the chip is not lying.” From that point on, I was fascinated with BIST.
In 1981, I was faced with designing a chip containing embedded RAM (a
CMOS standard cell device with 8K-bits of embedded RAM). I had heard horror stories
from other designers about the difficulty of writing vectors to test embedded
A Designer’s Guide to Built-In Self-Test
RAMs. I decided I would attempt to design a self-test circuit for the RAM to avoid
having to write the external test vectors. That is how I started working in BIST, being
fortunate to have been in the right place at the right time in the very early days of
BIST. I was also fortunate to be a bit naive, believing in BIST at a time when most
people did not think it would work. I designed a self-test circuit for embedded RAMs
which had a counter-based test pattern generator, a signature analysis-based output
response analyzer, and a counter-based test controller in my fourth chip. At a testability
review of the chip with Vishwani Agrawal and Ray Mercer from the Bell Labs at
Murray Hill, NJ, I presented the self-test circuit for the RAM for the first time. That
was also the first time I had met either Vishwani or Ray and I was overwhelmed by
their encouragement and support. The BIST circuit worked as planned when the chip
was fabricated and later was implemented in many more chips by other designers at
Bell Labs. Vishwani was working on an automated scan design system and had just
specified the scan support features in the automatic RAM generator for all standard
cell-based VLSI devices at Bell Labs. He suggested that the BIST option should also
be included in the RAM generator. After some refinements, the BIST circuitry was
integrated into the RAM generator by Duane Aadsen at Bell Labs in Allentown, PA.
My next BIST target was general sequential logic. I had studied the Built-In Logic
Block Observer (BILBO) with its problems of test scheduling and register self-adjacency
and I began to experiment with BILBO during a cost reduction redesign of one
of my high volume chips. I tried operating all BILBOs in the MISR mode of operation
during a single test session and achieved good fault coverage. Finding primitive
polynomials for the different size registers was a pain so I tried making one big
BILBO for the whole chip. When I couldn’t find a primitive polynomial for the big
BILBO, I removed the characteristic polynomial and by accident connected the output
of the last flip-flop to the input of the first, creating a circular chain of BIST flipflops.
The fault coverage was even higher than before and this BIST approach for
general sequential logic became known as Circular BIST and widely used in Bell
Labs. Incorporating both the logic BIST and RAM BIST approaches in the redesign
effort, this 1985 chip became the first completely self-testing chip at Bell Labs. In
1987, I worked on the first mixed-signal BIST approach at Bell Labs. I didn’t begin
publishing papers on any of this work until 1986 when Ed McCluskey of Stanford
University convinced me that other people would be interested.
I incorporated BIST circuitry of various types in 16 of the 21 chips I designed at Bell
Labs. I experimented with each new chip, trying different BIST approaches for different
types of circuits in different parts of the chips. I also helped other designers incorporate
BIST into many of their chips. As a result of the more than 30 production chips
I worked on that incorporated BIST, I learned a lot of valuable lessons with many of
these lessons learned through the hard knocks of making mistakes or failing to anticipate
certain issues that had not been considered before. These chips included gate
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Preface
array, standard cell, and full custom devices, with design rules from to
sizes ranging from about 10,000 to 400,000 transistors, and running at speeds
from 2MHz to 200MHz. While these chips are not large or fast by today’s standards,
they were pushing the limits of technology in terms of area and performance throughout
the 1980s and very early 1990s. In most of those chips, I made the BIST accessible
during system-level operation and testing. As a result, I was able to gain valuable
experience in all of the advantages (as well as many of the disadvantages) associated
with BIST and system-level use of BIST. Since leaving Bell Labs, I have continued
research and development of BIST for digital and mixed-signal VLSI as well as BIST
for CPLDs and FPGAs. This work has been funded by AT&T Bell Laboratories,
Lucent Technologies, Agere Systems, Cypress Semiconductor, NSF, DARPA, NSA,
US Air Force, and the US Army.
One of the aspects of BIST that I enjoyed the most was that, while I designed the system
function for the good of the project according to system specifications, I designed
the BIST circuitry for myself according to my specifications. The primary reason for
incorporating BIST in my early chip designs was to save myself a lot of time and
effort in test vector development. That continued to be my goal in later chips as well,
even when BIST capabilities were sought by system diagnostic software developers.
While I enjoyed the creativity and satisfaction of designing the system function to
meet the system requirements, I found the creativity and satisfaction of BIST design
even more enjoyable since it was something I was designing for myself. The ability to
use the BIST approach for the good of the project to reduce manufacturing and system-
level testing time and cost was simply ‘icing on the cake’.
This book is primarily intended for designers, test engineers, product engineers, system
diagnosticians, and managers. Many engineers have heard about BIST but are not
quite sure what it is, how it works, or if and how they should go about applying it to
their system. Other engineers know some of the basics of BIST but are not familiar
with all of the techniques and issues. Twenty years ago I would have loved to see a
book entitled “BIST for the Grunts in the Trenches” that gave a simple, but fair treatment
of BIST at all levels of testing. While there are some good books on testing and
DFT that also discuss BIST, there has been only one book that focuses on BIST [32].
As a designer, I found it difficult to wade through the theory and math. As a result,
this book is not primarily intended to be a classroom textbook with lots of theory, but
rather a book to help the practicing engineer with examples and discussion of some of
the key issues they face. For students reading this book, I hope that this book can offer
some valuable insight into the issues and considerations that practicing engineers and
managers must address. Background chapters are included that contain an overview
of fault modeling, detection, and simulation (Chapter 2) and design for testability
(Chapter 3) for those that have limited background in testing. However, these chapters
also contain information that is essential to a complete understanding and effixiii
A Designer’s Guide to Built-In Self-Test
cient implementation of BIST. I also include footnotes throughout that contain tidbits,
tips, and “war” stories that I have encountered in my years working with BIST.
Just as Vishwani Agrawal (Agere Systems, formerly Bell Labs) and Ray Mercer
(Texas A&M Univ., formerly with Bell Labs) had a big influence on my BIST career,
there were several others who encouraged my BIST work along the way. Since this
book is largely a result of the influence of these good people, it is only proper to
acknowledge them. They include: Harry Kalvonjian (Agere Systems, formerly Bell
Labs), Ed McCluskey (Stanford Univ.), Tom Williams (Synopsys, formerly with
IBM), Jacob Abraham (Univ. of Texas - Austin, formerly with Univ. of Illinois),
Jacob Savir (New Jersey Institute of Technology, formerly with IBM), Vinod Agarwal
(President/CEO of LogicVision, formerly with McGill Univ.) and last but certainly
not least, Miron Abramovici (Agere Systems, formerly Bell Labs). Finally,
most of us owe a great deal to those professors that took the interest and time to shape
our lives for the better through our undergraduate and graduate studies. For me they
include: Gene Bradley, Ray Distler, and Chun Ro (all are Professor Emeritus of Univ.
of Kentucky), and my undergraduate and MSEE advisor at Univ. of Kentucky, Lee
Todd (President of Univ. of Kentucky, formerly President/CEO of DataBeam).
I have been fortunate over the past 10 years to work with outstanding undergraduate
and graduate students in BIST related research and development. Since some of the
material in this book is a result of our time spent together, they include: Jamie Bailey,
Ping Chen, Chandan Das, Ming Ding, Travis Ferry, Gretchen Gibson, Carter Hamilton,
Ping He, Piyumani Karunaratna, Varma Konala, Matt Lashinsky, Eric Lee, Brandon
Lewis, Wai Khuan Long, Kristi Maggard, Jeremy Nall, Bob Puckett, Andy Russ,
Kripa Sankarananayanan, Brandon Skaggs, Thomas Slaughter, Shannon Spencer,
Malissa Sullivan, Joe Tannehill, Andrew Taylor, Stan Tungate, Nick Vocke, Sajitha
Wijesuriya, and Yingchang Yang.
I would like to thank the people that assisted in preparing this book: my wife Ramona;
Matt Lashinsky, Chris Mays, and Jeremy Nall (students at UNC-Charlotte); Miron
Abramovici (Bell Labs, Murray Hill, NJ), Loren Charnley (Managing Partner, Dyna-
Zign, Inc., Charlotte, NC), and Rafic Makki (UNC-Charlotte). A special thanks to
Carl Harris of Kluwer Academic Publishers for encouraging me to pursue this book.
Finally, it was pleasantly ironic and appropriate to have Vishwani Agrawal as the
consulting editor; my sincerest thanks to Vishwani for his guidance in this effort as
well as for his being a role model for twenty years.
Charles E. Stroud, Professor
Dept. of Electrical & Computer Engineering
University of North Carolina at Charlotte