A Computer-Aided Design and Synthesis Environment for Analog Integrated Circuits: A Computer-Aided Design and Synthesis Environment for Analog Integrated Circuits.jpg

送上一本书，作为庆祝本站突破41万帖



A COMPUTER-AIDED DESIGN
AND SYNTHESIS
ENVIRONMENT FOR ANALOG
INTEGRATED CIRCUITS
by
Geert Van der Plas
KU Leuven
Georges Gielen
KU Leuven
and
Willy Sansen
KU Leuven
KLUWER ACADEMIC PUBLISHERS
NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW

Contents
Abstract
List of Abbreviations
List of Symbols
Contents
List of Figures
List of Tables
i
iii
v
ix
xiii
xvii
1 Introduction
1.1 Goals of this Work
1.2 Outline of this Work
1
9
11
I Automatic Synthesis of Analog Circuits 13
2 The AMGIE Analog Synthesis System
2.1 Introduction
2.2 Definitions
2.3 Overview of Analog Synthesis Research
2.3.1 Early Work
2.3.2 Second Generation
2.3.3 Most Recent Work
2.3.4 Conclusions
2.4 The AMGIE Synthesis System
2.4.1 Functionality of the Analog Synthesis Environment
2.4.2 Software Architecture of the AMGIE System
2.5 Summary
15
15
15
19
20
21
23
25
26
26
34
38
3 Detailed Description of the AMGIE Analog Synthesis System 39
39
42
42
3.1
3.2
Specifications and Hierarchy
Topology Selection Tool
3.2.1 Boundary Checking Filter
x Contents
3.2.2
3.2.3
Interval Analysis Filter
Rule-based Ranking Filter
3.3 Sizing and Optimization Tool
3.3.1
3.3.2
3.3.3
Sizing Model Generation
Circuit Optimization Setup
Practical Example
44
45
45
47
55
57
61
64
65
66
69
70
70
70
71
73
73
74
74
75
76
77
79
79
79
86
89
90
91
92
101
102
102
106
106
107
108
109
113
Introduction 115
II Systematic Design of Analog Circuits
Conclusions
3.4 Layout Generation Tool
3.4.1 Practical Example
3.5 Verification Tool
3.5.1
3.5.2
3.5.3
Nominal Performance Verification
Verification with Mismatches and Technology Spread
Verification over Temperature and Power-supply Operating Ranges
3.6 Redesign Wizard
3.6.1 Example Scenarios
3.7 Summary
4 AMGIE Experimental Results
4.1 Comparison of Analog Sizing Synthesis: Equation-based vs. Simulation-based
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
Design Specifications
Manual Sizing
Simulation-based Sizing
Equation-based Sizing
Comparison & Conclusions
4.2 Student Exercise: High-speed Operational Transconductance Amplifier
4.2.1 Setup
4.2.2 Session
4.2.3 Analysis of Results
4.2.4 Conclusions
4.3 Charge-Sensitive Amplifier – Pulse-Shaping Amplifier
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.3.8
CSA-PSA Specifications
CSA-PSA Architecture
Topology Selection
Sizing Synthesis: OPTlMAN
Layout Generation
Verification
Measurement Results
Conclusions
4.4 Summary
Contents xi
5 Mondriaan: a Layout Synthesis Methodology for Array-type Analog Blocks
5.1
5.2
5.3
Requirements of the New Layout Generation Methodology
Description of the Layout Model
Description of the Layout Generation Methodology
5.3.1
5.3.2
5.3.3
5.3.4
Floorplanning
Symbolic Routing
Technology Mapping
Bus and Tree Generators
117
119
120
123
124
125
126
127
130
130
133
135
136
137
137
140
143
145
146
148
148
149
152
152
154
154
156
156
159
161
163
163
163
164
176
177
177
178
178
179
181
181
182
184
5.4 Illustrative Example
5.4.1 Current Source Array
5.4.2 Switch/Latch Array
5.4.3 Assembly
5.4.4 Conclusions
5.5 Experimental Results
5.5.1
5.5.2
Folding/Interpolating A/D-converter Modules
Current-Steering D/A-converter Modules
5.6 Conclusions
6 Systematic Design of Current-Steering D/A-converters
6.1
6.2
Functionblock Design Flow
Current-Steering D/A-converter Architecture
6.2.1 Operating Principle and Specifications
6.2.2 Proposed Architecture and its Design Parameters
6.3 Behavioral Modeling for the Specification Phase
6.3.1
6.3.2
Dynamic Behavior
Static Behavior
6.4 Synthesis Flow of the D/A-converter
6.5 Sizing Synthesis
6.5.1
6.5.2
6.5.3
6.5.4
Architectural-level Synthesis
Circuit-level Synthesis
Full Decoder Synthesis
Clock Driver Synthesis
6.6 Layout Generation
6.6.1
6.6.2
6.6.3
6.6.4
6.6.5
Floorplanning
Current Source Array Layout Generation
Swatch Array Layout Generation
Full Decoder Standard Cell Place and Route
Layout Assembly
6.7 Extraction of a Behavioral Model for Verification
6.7.1
6.7.2
Static Behavior: INL
Dynamic Behavior: Glitch Energy
6.8 Experimental Results
6.8.1 Measurement Setup
6.8.2
6.8.3
Measurement Results
Breakdown of Design Time
xii Contents
6.9 Conclusions
7 Conclusions
186
189
193
205
Bibliography
Index

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