SiC Substrate Via Etch Process Optimization: SiC Substrate Via Etch Process Optimization.pdf

SiC Substrate Via Etch Process Optimization
Presented at the 2009 CS Mantech Conference, Tampa, FLorida
Ju-Ai Ruan, Sam Roadman, Cathy Lee, Cary Sellers, Mike Regan May 2009, 3 pages.

SiC etch rates and etch selectivity to GaN have been studied under a range of RF plasma power conditions. Slightly higher etch rate and higher etch selectivity were obtained at increased coil RF power. Higher etch rate was also obtained at increased platen RF power, but at the sacrifice of decreasing etch selectivity. Substantial pillar formation was observed when coil RF power is below certain limit. Pillar formation during SiC etches due to variation of process conditions was also studied with methods to reduce pillar formation discussed. We observed that by properly modifying pre-etch clean and etch processes, systematic pillar formation can be avoided.