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Analog.Integrated.Circuit.Design.Martin.Johns.Martin,.Carusone.2ed【2012新书】

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  31. Library of Congress Cataloging-in-Publication Data
  32. Carusone, Tony Chan.
  33. Analog integrated circuit design / Tony Chan Carusone, David A. Johns, Kenneth W. Martin. —2nd ed.
  34. p. cm.
  35. Includes index.
  36. Prev ed. listed under David A. Johns.
  37. ISBN 978-0-470-77010-8 (pbk.)
  38. I. Johns, David, 1958 II. Martin, Kenneth W. (Kenneth William) 1952 III. Johns, David, 1958- Analog
  39. integrated circuit design. IV. Title.
  40. TK7874.J65 2011
  41. 621.3815—dc23
  42. 2011039275
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  1. CHAPTER 1 INTEGRATED-CIRCUIT DEVICES AND MODELLING 1
  2. 1.1 Semiconductors and pn Junctions 1
  3. 1.1.1 Diodes 2
  4. 1.1.2 Reverse-Biased Diodes 4
  5. 1.1.3 Graded Junctions 7
  6. 1.1.4 Large-Signal Junction Capacitance 9
  7. 1.1.5 Forward-Biased Junctions 10
  8. 1.1.6 Junction Capacitance of Forward-Biased Diode 11
  9. 1.1.7 Small-Signal Model of a Forward-Biased Diode 12
  10. 1.1.8 Schottky Diodes 13
  11. 1.2 MOS Transistors 14
  12. 1.2.1 Symbols for MOS Transistors 15
  13. 1.2.2 Basic Operation 16
  14. 1.2.3 Large-Signal Modelling 21
  15. 1.2.4 Body Effect 24
  16. 1.2.5 p-Channel Transistors 24
  17. 1.2.6 Low-Frequency Small-Signal Modelling in the Active Region 25
  18. 1.2.7 High-Frequency Small-Signal Modelling in the Active Region 30
  19. 1.2.8 Small-Signal Modelling in the Triode and Cutoff Regions 33
  20. 1.2.9 Analog Figures of Merit and Trade-offs 36
  21. 1.3 Device Model Summary 38
  22. 1.3.1 Constants 38
  23. 1.3.2 Diode Equations 39
  24. 1.3.3 MOS Transistor Equations 40
  25. 1.4 Advanced MOS Modelling 42
  26. 1.4.1 Subthreshold Operation 42
  27. 1.4.2 Mobility Degradation 44
  28. 1.4.3 Summary of Subthreshold and Mobility Degradation Equations 47
  29. 1.4.4 Parasitic Resistances 47
  30. 1.4.5 Short-Channel Effects 48
  31. 1.4.6 Leakage Currents 49
  32. 1.5 SPICE Modelling Parameters 50
  33. 1.5.1 Diode Model 50
  34. 1.5.2 MOS Transistors 51
  35. 1.5.3 Advanced SPICE Models of MOS Transistors 51
  36. 1.6 Passive Devices 54
  37. 1.6.1 Resistors 54
  38. 1.6.2 Capacitors 58
  39. Contents
  40. xii Contents
  41. 1.7 Appendix 60
  42. 1.7.1 Diode Exponential Relationship 60
  43. 1.7.2 Diode-Diffusion Capacitance 62
  44. 1.7.3 MOS Threshold Voltage and the Body Effect 64
  45. 1.7.4 MOS Triode Relationship 66
  46. 1.8 Key Points 68
  47. 1.9 References 69
  48. 1.10 Problems 69
  49. CHAPTER 2 PROCESSING AND LAYOUT 73
  50. 2.1 CMOS Processing 73
  51. 2.1.1 The Silicon Wafer 73
  52. 2.1.2 Photolithography and Well Definition 74
  53. 2.1.3 Diffusion and Ion Implantation 76
  54. 2.1.4 Chemical Vapor Deposition and Defining the Active Regions 78
  55. 2.1.5 Transistor Isolation 78
  56. 2.1.6 Gate-Oxide and Threshold-Voltage Adjustments 81
  57. 2.1.7 Polysilicon Gate Formation 82
  58. 2.1.8 Implanting the Junctions, Depositing SiO2, and Opening
  59. Contact Holes 82
  60. 2.1.9 Annealing, Depositing and Patterning Metal, and Overglass
  61. Deposition 84
  62. 2.1.10 Additional Processing Steps 84
  63. 2.2 CMOS Layout and Design Rules 86
  64. 2.2.1 Spacing Rules 86
  65. 2.2.2 Planarity and Fill Requirements 94
  66. 2.2.3 Antenna Rules 94
  67. 2.2.4 Latch-Up 95
  68. 2.3 Variability and Mismatch 96
  69. 2.3.1 Systematic Variations Including Proximity Effects 96
  70. 2.3.2 Process Variations 98
  71. 2.3.3 Random Variations and Mismatch 99
  72. 2.4 Analog Layout Considerations 103
  73. 2.4.1 Transistor Layouts 103
  74. 2.4.2 Capacitor Matching 104
  75. 2.4.3 Resistor Layout 107
  76. 2.4.4 Noise Considerations 109
  77. 2.5 Key Points 113
  78. 2.6 References 114
  79. 2.7 Problems 114
  80. CHAPTER 3 BASIC CURRENT MIRRORS AND SINGLE-STAGE AMPLIFIERS 117
  81. 3.1 Simple CMOS Current Mirror 118
  82. 3.2 Common-Source Amplifier 120
  83. 3.3 Source-Follower or Common-Drain Amplifier 122
  84. Contents xiii
  85. 3.4 Common-Gate Amplifier 124
  86. 3.5 Source-Degenerated Current Mirrors 127
  87. 3.6 Cascode Current Mirrors 129
  88. 3.7 Cascode Gain Stage 131
  89. 3.8 MOS Differential Pair and Gain Stage 135
  90. 3.9 Key Points 138
  91. 3.10 References 139
  92. 3.11 Problems 139
  93. CHAPTER 4 FREQUENCY RESPONSE OF ELECTRONIC CIRCUITS 144
  94. 4.1 Frequency Response of Linear Systems 144
  95. 4.1.1 Magnitude and Phase Response 145
  96. 4.1.2 First-Order Circuits 147
  97. 4.1.3 Second-Order Low-Pass Transfer Functions with Real Poles 154
  98. 4.1.4 Bode Plots 157
  99. 4.1.5 Second-Order Low-Pass Transfer Functions with Complex Poles 163
  100. 4.2 Frequency Response of Elementary Transistor Circuits 165
  101. 4.2.1 High-Frequency MOS Small-Signal Model 165
  102. 4.2.2 Common-Source Amplifier 166
  103. 4.2.3 Miller Theorem and Miller Effect 169
  104. 4.2.4 Zero-Value Time-Constant Analysis 173
  105. 4.2.5 Common-Source Design Examples 176
  106. 4.2.6 Common-Gate Amplifier 179
  107. 4.3 Cascode Gain Stage 181
  108. 4.4 Source-Follower Amplifier 187
  109. 4.5 Differential Pair 193
  110. 4.5.1 High-Frequency T-Model 193
  111. 4.5.2 Symmetric Differential Amplifier 194
  112. 4.5.3 Single-Ended Differential Amplifier 195
  113. 4.5.4 Differential Pair with Active Load 196
  114. 4.6 Key Points 197
  115. 4.7 References 198
  116. 4.8 Problems 199
  117. CHAPTER 5 FEEDBACK AMPLIFIERS 204
  118. 5.1 Ideal Model of Negative Feedback 204
  119. 5.1.1 Basic Definitions 204
  120. 5.1.2 Gain Sensitivity 205
  121. 5.1.3 Bandwidth 207
  122. 5.1.4 Linearity 207
  123. 5.1.5 Summary 208
  124. 5.2 Dynamic Response of Feedback Amplifiers 208
  125. 5.2.1 Stability Criteria 209
  126. 5.2.2 Phase Margin 211
  127. xiv Contents
  128. 5.3 First- and Second-Order Feedback Systems 213
  129. 5.3.1 First-Order Feedback Systems 213
  130. 5.3.2 Second-Order Feedback Systems 217
  131. 5.3.3 Higher-Order Feedback Systems 220
  132. 5.4 Common Feedback Amplifiers 220
  133. 5.4.1 Obtaining the Loop Gain, L(s) 222
  134. 5.4.2 Non-Inverting Amplifier 226
  135. 5.4.3 Transimpedance (Inverting) Amplifiers 231
  136. 5.5 Summary of Key Points 235
  137. 5.6 References 235
  138. 5.7 Problems 236
  139. CHAPTER 6 BASIC OPAMP DESIGN AND COMPENSATION 242
  140. 6.1 Two-Stage CMOS Opamp 242
  141. 6.1.1 Opamp Gain 243
  142. 6.1.2 Frequency Response 245
  143. 6.1.3 Slew Rate 249
  144. 6.1.4 n-Channel or p-Channel Input Stage 252
  145. 6.1.5 Systematic Offset Voltage 252
  146. 6.2 Opamp Compensation 254
  147. 6.2.1 Dominant-Pole Compensation and Lead Compensation 254
  148. 6.2.2 Compensating the Two-Stage Opamp 255
  149. 6.2.3 Making Compensation Independent of Process and Temperature 259
  150. 6.3 Advanced Current Mirrors 261
  151. 6.3.1 Wide-Swing Current Mirrors 261
  152. 6.3.2 Enhanced Output-Impedance Current Mirrors and Gain Boosting 263
  153. 6.3.3 Wide-Swing Current Mirror with Enhanced Output Impedance 266
  154. 6.3.4 Current-Mirror Symbol 267
  155. 6.4 Folded-Cascode Opamp 268
  156. 6.4.1 Small-Signal Analysis 270
  157. 6.4.2 Slew Rate 272
  158. 6.5 Current Mirror Opamp 275
  159. 6.6 Linear Settling Time Revisited 279
  160. 6.7 Fully Differential Opamps 281
  161. 6.7.1 Fully Differential Folded-Cascode Opamp 283
  162. 6.7.2 Alternative Fully Differential Opamps 284
  163. 6.7.3 Low Supply Voltage Opamps 286
  164. 6.8 Common-Mode Feedback Circuits 288
  165. 6.9 Summary of Key Points 292
  166. 6.10 References 293
  167. 6.11 Problems 294
  168. CHAPTER 7 BIASING, REFERENCES, AND REGULATORS 302
  169. 7.1 Analog Integrated Circuit Biasing 302
  170. 7.1.1 Bias Circuits 303
  171. Contents xv
  172. 7.1.2 Reference Circuits 305
  173. 7.1.3 Regulator Circuits 306
  174. 7.2 Establishing Constant Transconductance 307
  175. 7.2.1 Basic Constant-Transconductance Circuit 307
  176. 7.2.2 Improved Constant-Transconductance Circuits 309
  177. 7.3 Establishing Constant Voltages and Currents 310
  178. 7.3.1 Bandgap Voltage Reference Basics 310
  179. 7.3.2 Circuits for Bandgap References 314
  180. 7.3.3 Low-Voltage Bandgap Reference 319
  181. 7.3.4 Current Reference 320
  182. 7.4 Voltage Regulation 321
  183. 7.4.1 Regulator Specifications 322
  184. 7.4.2 Feedback Analysis 322
  185. 7.4.3 Low Dropout Regulators 324
  186. 7.5 Summary of Key Points 327
  187. 7.6 References 327
  188. 7.7 Problems 328
  189. CHAPTER 8 BIPOLAR DEVICES AND CIRCUITS 331
  190. 8.1 Bipolar-Junction Transistors 331
  191. 8.1.1 Basic Operation 331
  192. 8.1.2 Analog Figures of Merit 341
  193. 8.2 Bipolar Device Model Summary 344
  194. 8.3 SPICE Modeling 345
  195. 8.4 Bipolar and BICMOS Processing 346
  196. 8.4.1 Bipolar Processing 346
  197. 8.4.2 Modern SiGe BiCMOS HBT Processing 347
  198. 8.4.3 Mismatch in Bipolar Devices 348
  199. 8.5 Bipolar Current Mirrors and Gain Stages 349
  200. 8.5.1 Current Mirrors 349
  201. 8.5.2 Emitter Follower 350
  202. 8.5.3 Bipolar Differential Pair 353
  203. 8.6 Appendix 356
  204. 8.6.1 Bipolar Transistor Exponential Relationship 356
  205. 8.6.2 Base Charge Storage of an Active BJT 359
  206. 8.7 Summary of Key Points 359
  207. 8.8 References 360
  208. 8.9 Problems 360
  209. CHAPTER 9 NOISE AND LINEARITY ANALYSIS AND MODELLING 363
  210. 9.1 Time-Domain Analysis 363
  211. 9.1.1 Root Mean Square (rms) Value 364
  212. 9.1.2 SNR 365
  213. 9.1.3 Units of dBm 365
  214. 9.1.4 Noise Summation 366
  215. xvi Contents
  216. 9.2 Frequency-Domain Analysis 367
  217. 9.2.1 Noise Spectral Density 367
  218. 9.2.2 White Noise 369
  219. 9.2.3 1/f, or Flicker, Noise 370
  220. 9.2.4 Filtered Noise 371
  221. 9.2.5 Noise Bandwidth 373
  222. 9.2.6 Piecewise Integration of Noise 375
  223. 9.2.7 1/f Noise Tangent Principle 377
  224. 9.3 Noise Models for Circuit Elements 377
  225. 9.3.1 Resistors 378
  226. 9.3.2 Diodes 378
  227. 9.3.3 Bipolar Transistors 380
  228. 9.3.4 MOSFETS 380
  229. 9.3.5 Opamps 382
  230. 9.3.6 Capacitors and Inductors 382
  231. 9.3.7 Sampled Signal Noise 384
  232. 9.3.8 Input-Referred Noise 384
  233. 9.4 Noise Analysis Examples 387
  234. 9.4.1 Opamp Example 387
  235. 9.4.2 Bipolar Common-Emitter Example 390
  236. 9.4.3 CMOS Differential Pair Example 392
  237. 9.4.4 Fiber-Optic Transimpedance Amplifier Example 395
  238. 9.5 Dynamic Range Performance 397
  239. 9.5.1 Total Harmonic Distortion (THD) 398
  240. 9.5.2 Third-Order Intercept Point (IP3) 400
  241. 9.5.3 Spurious-Free Dynamic Range (SFDR) 402
  242. 9.5.4 Signal-to-Noise and Distortion Ratio (SNDR) 404
  243. 9.6 Key Points 405
  244. 9.7 References 406
  245. 9.8 Problems 406
  246. CHAPTER 10 COMPARATORS 413
  247. 10.1 Comparator Specifications 413
  248. 10.1.1 Input Offset and Noise 413
  249. 10.1.2 Hysteresis 414
  250. 10.2 Using an Opamp for a Comparator 415
  251. 10.2.1 Input-Offset Voltage Errors 417
  252. 10.3 Charge-Injection Errors 418
  253. 10.3.1 Making Charge-Injection Signal Independent 421
  254. 10.3.2 Minimizing Errors Due to Charge-Injection 421
  255. 10.3.3 Speed of Multi-Stage Comparators 424
  256. 10.4 Latched Comparators 426
  257. 10.4.1 Latch-Mode Time Constant 427
  258. 10.4.2 Latch Offset 430
  259. Contents xvii
  260. 10.5 Examples of CMOS and BiCMOS Comparators 431
  261. 10.5.1 Input-Transistor Charge Trapping 435
  262. 10.6 Examples of Bipolar Comparators 437
  263. 10.7 Key Points 439
  264. 10.8 References 440
  265. 10.9 Problems 440
  266. CHAPTER 11 SAMPLE-AND-HOLD AND TRANSLINEAR CIRCUITS 444
  267. 11.1 Performance of Sample-and-Hold Circuits 444
  268. 11.1.1 Testing Sample and Holds 445
  269. 11.2 MOS Sample-and-Hold Basics 446
  270. 11.3 Examples of CMOS S/H Circuits 452
  271. 11.4 Bipolar and BiCMOS Sample-and-Holds 456
  272. 11.5 Translinear Gain Cell 460
  273. 11.6 Translinear Multiplier 462
  274. 11.7 Key Points 464
  275. 11.8 References 465
  276. 11.9 Problems 466
  277. CHAPTER 12 CONTINUOUS-TIME FILTERS 469
  278. 12.1 Introduction to Continuous-Time Filters 469
  279. 12.1.1 First-Order Filters 470
  280. 12.1.2 Second-Order Filters 470
  281. 12.2 Introduction to Gm-C Filters 471
  282. 12.2.1 Integrators and Summers 472
  283. 12.2.2 Fully Differential Integrators 474
  284. 12.2.3 First-Order Filter 475
  285. 12.2.4 Biquad Filter 477
  286. 12.3 Transconductors Using Fixed Resistors 479
  287. 12.4 CMOS Transconductors Using Triode Transistors 484
  288. 12.4.1 Transconductors Using a Fixed-Bias Triode Transistor 484
  289. 12.4.2 Transconductors Using Varying Bias-Triode Transistors 486
  290. 12.4.3 Transconductors Using Constant Drain-Source Voltages 491
  291. 12.5 CMOS Transconductors Using Active Transistors 493
  292. 12.5.1 CMOS Pair 493
  293. 12.5.2 Constant Sum of Gate-Source Voltages 494
  294. 12.5.3 Source-Connected Differential Pair 495
  295. 12.5.4 Inverter-Based 495
  296. 12.5.5 Differential-Pair with Floating Voltage Sources 497
  297. 12.5.6 Bias-Offset Cross-Coupled Differential Pairs 499
  298. 12.6 Bipolar Transconductors 500
  299. 12.6.1 Gain-Cell Transconductors 500
  300. 12.6.2 Transconductors Using Multiple Differential Pairs 501
  301. xviii Contents
  302. 12.7 BiCMOS Transconductors 506
  303. 12.7.1 Tunable MOS in Triode 506
  304. 12.7.2 Fixed-Resistor Transconductor with a Translinear Multiplier 507
  305. 12.7.3 Fixed Active MOS Transconductor with a Translinear
  306. Multiplier 508
  307. 12.8 Active RC and MOSFET-C Filters 509
  308. 12.8.1 Active RC Filters 510
  309. 12.8.2 MOSFET-C Two-Transistor Integrators 512
  310. 12.8.3 Four-Transistor Integrators 515
  311. 12.8.4 R-MOSFET-C Filters 521
  312. 12.9 Tuning Circuitry 516
  313. 12.9.1 Tuning Overview 517
  314. 12.9.2 Constant Transconductance 519
  315. 12.9.3 Frequency Tuning 520
  316. 12.9.4 Q-Factor Tuning 522
  317. 12.9.5 Tuning Methods Based on Adaptive Filtering 523
  318. 12.10 Introduction to Complex Filters 525
  319. 12.10.1 Complex Signal Processing 525
  320. 12.10.2 Complex Operations 526
  321. 12.10.3 Complex Filters 527
  322. 12.10.4 Frequency-Translated Analog Filters 528
  323. 12.11 Key Points 531
  324. 12.12 References 532
  325. 12.13 Problems 534
  326. CHAPTER 13 DISCRETE-TIME SIGNALS 537
  327. 13.1 Overview of Some Signal Spectra 537
  328. 13.2 Laplace Transforms of Discrete-Time Signals 537
  329. 13.2.1 Spectra of Discrete-Time Signals 540
  330. 13.3 z-Transform 541
  331. 13.4 Downsampling and Upsampling 543
  332. 13.5 Discrete-Time Filters 545
  333. 13.5.1 Frequency Response of Discrete-Time Filters 545
  334. 13.5.2 Stability of Discrete-Time Filters 548
  335. 13.5.3 IIR and FIR Filters 550
  336. 13.5.4 Bilinear Transform 550
  337. 13.6 Sample-and-Hold Response 552
  338. 13.7 Key Points 554
  339. 13.8 References 555
  340. 13.9 Problems 555
  341. CHAPTER 14 SWITCHED-CAPACITOR CIRCUITS 557
  342. 14.1 Basic Building Blocks 557
  343. 14.1.1 Opamps 557
  344. Contents xix
  345. 14.1.2 Capacitors 558
  346. 14.1.3 Switches 558
  347. 14.1.4 Nonoverlapping Clocks 559
  348. 14.2 Basic Operation and Analysis 560
  349. 14.2.1 Resistor Equivalence of a Switched Capacitor 560
  350. 14.2.2 Parasitic-Sensitive Integrator 560
  351. 14.2.3 Parasitic-Insensitive Integrators 565
  352. 14.2.4 Signal-Flow-Graph Analysis 569
  353. 14.3 Noise in Switched-Capacitor Circuits 570
  354. 14.4 First-Order Filters 572
  355. 14.4.1 Switch Sharing 575
  356. 14.4.2 Fully Differential Filters 575
  357. 14.5 Biquad Filters 577
  358. 14.5.1 Low-Q Biquad Filter 577
  359. 14.5.2 High-Q Biquad Filter 581
  360. 14.6 Charge Injection 585
  361. 14.7 Switched-Capacitor Gain Circuits 588
  362. 14.7.1 Parallel Resistor-Capacitor Circuit 588
  363. 14.7.2 Resettable Gain Circuit 588
  364. 14.7.3 Capacitive-Reset Gain Circuit 591
  365. 14.8 Correlated Double-Sampling Techniques 593
  366. 14.9 Other Switched-Capacitor Circuits 594
  367. 14.9.1 Amplitude Modulator 594
  368. 14.9.2 Full-Wave Rectifier 595
  369. 14.9.3 Peak Detectors 596
  370. 14.9.4 Voltage-Controlled Oscillator 596
  371. 14.9.5 Sinusoidal Oscillator 598
  372. 14.10 Key Points 600
  373. 14.11 References 601
  374. 14.12 Problems 602
  375. CHAPTER 15 DATA CONVERTER FUNDAMENTALS 606
  376. 15.1 Ideal D/A Converter 606
  377. 15.2 Ideal A/D Converter 608
  378. 15.3 Quantization Noise 609
  379. 15.3.1 Deterministic Approach 609
  380. 15.3.2 Stochastic Approach 610
  381. 15.4 Signed Codes 612
  382. 15.5 Performance Limitations 614
  383. 15.5.1 Resolution 614
  384. 15.5.2 Offset and Gain Error 615
  385. 15.5.3 Accuracy and Linearity 615
  386. 15.6 Key Points 620
  387. 15.7 References 620
  388. 15.8 Problems 620
  389. xx Contents
  390. CHAPTER 16 NYQUIST-RATE D/A CONVERTERS 623
  391. 16.1 Decoder-Based Converters 623
  392. 16.1.1 Resistor String Converters 623
  393. 16.1.2 Folded Resistor-String Converters 625
  394. 16.1.3 Multiple Resistor-String Converters 625
  395. 16.1.4 Signed Outputs 627
  396. 16.2 Binary-Scaled Converters 628
  397. 16.2.1 Binary-Weighted Resistor Converters 629
  398. 16.2.2 Reduced-Resistance-Ratio Ladders 630
  399. 16.2.3 R-2R-Based Converters 630
  400. 16.2.4 Charge-Redistribution Switched-Capacitor Converters 632
  401. 16.2.5 Current-Mode Converters 633
  402. 16.2.6 Glitches 633
  403. 16.3 Thermometer-Code Converters 634
  404. 16.3.1 Thermometer-Code Current-Mode D/A Converters 636
  405. 16.3.2 Single-Supply Positive-Output Converters 637
  406. 16.3.3 Dynamically Matched Current Sources 638
  407. 16.4 Hybrid Converters 640
  408. 16.4.1 Resistor-Capacitor Hybrid Converters 640
  409. 16.4.2 Segmented Converters 640
  410. 16.5 Key Points 642
  411. 16.6 References 643
  412. 16.7 Problems 643
  413. CHAPTER 17 NYQUIST-RATE A/D CONVERTERS 646
  414. 17.1 Integrating Converters 646
  415. 17.2 Successive-Approximation Converters 650
  416. 17.2.1 DAC-Based Successive Approximation 652
  417. 17.2.2 Charge-Redistribution A/D 653
  418. 17.2.3 Resistor-Capacitor Hybrid 658
  419. 17.2.4 Speed Estimate for Charge-Redistribution Converters 658
  420. 17.2.5 Error Correction in Successive-Approximation Converters 659
  421. 17.2.6 Multi-Bit Successive-Approximation 662
  422. 17.3 Algorithmic (or Cyclic) A/D Converter 662
  423. 17.3.1 Ratio-Independent Algorithmic Converter 662
  424. 17.4 Pipelined A/D Converters 665
  425. 17.4.1 One-Bit-Per-Stage Pipelined Converter 667
  426. 17.4.2 1.5 Bit Per Stage Pipelined Converter 669
  427. 17.4.3 Pipelined Converter Circuits 672
  428. 17.4.4 Generalized k-Bit-Per-Stage Pipelined Converters 673
  429. 17.5 Flash Converters 673
  430. 17.5.1 Issues in Designing Flash A/D Converters 675
  431. 17.6 Two-Step A/D Converters 677
  432. 17.6.1 Two-Step Converter with Digital Error Correction 679
  433. 17.7 Interpolating A/D Converters 680
  434. Contents xxi
  435. 17.8 Folding A/D Converters 683
  436. 17.9 Time-Interleaved A/D Converters 687
  437. 17.10 Key Points 690
  438. 17.11 References 691
  439. 17.12 Problems 692
  440. CHAPTER 18 OVERSAMPLING CONVERTERS 696
  441. 18.1 Oversampling without Noise Shaping 696
  442. 18.1.1 Quantization Noise Modelling 697
  443. 18.1.2 White Noise Assumption 697
  444. 18.1.3 Oversampling Advantage 699
  445. 18.1.4 The Advantage of 1-Bit D/A Converters 701
  446. 18.2 Oversampling with Noise Shaping 702
  447. 18.2.1 Noise-Shaped Delta-Sigma Modulator 703
  448. 18.2.2 First-Order Noise Shaping 704
  449. 18.2.3 Switched-Capacitor Realization of a First-Order A/D Converter 706
  450. 18.2.4 Second-Order Noise Shaping 706
  451. 18.2.5 Noise Transfer-Function Curves 708
  452. 18.2.6 Quantization Noise Power of 1-Bit Modulators 709
  453. 18.2.7 Error-Feedback Structure 709
  454. 18.3 System Architectures 711
  455. 18.3.1 System Architecture of Delta-Sigma A/D Converters 711
  456. 18.3.2 System Architecture of Delta-Sigma D/A Converters 713
  457. 18.4 Digital Decimation Filters 714
  458. 18.4.1 Multi-Stage 715
  459. 18.4.2 Single Stage 717
  460. 18.5 Higher-Order Modulators 718
  461. 18.5.1 Interpolative Architecture 718
  462. 18.5.2 Multi-Stage Noise Shaping (MASH) Architecture 719
  463. 18.6 Bandpass Oversampling Converters 721
  464. 18.7 Practical Considerations 722
  465. 18.7.1 Stability 722
  466. 18.7.2 Linearity of Two-Level Converters 723
  467. 18.7.3 Idle Tones 725
  468. 18.7.4 Dithering 726
  469. 18.7.5 Opamp Gain 726
  470. 18.8 Multi-Bit Oversampling Converters 727
  471. 18.8.1 Dynamic Element Matching 727
  472. 18.8.2 Dynamically Matched Current Source D/S Converters 728
  473. 18.8.3 Digital Calibration A/D Converter 728
  474. 18.8.4 A/D with Both Multi-Bit and Single-Bit Feedback 729
  475. 18.9 Third-Order A/D Design Example 730
  476. 18.10 Key Points 732
  477. 18.11 References 734
  478. 18.12 Problems 735
  479. xxii Contents
  480. CHAPTER 19 PHASE-LOCKED LOOPS 738
  481. 19.1 Basic Phase-Locked Loop Architecture 738
  482. 19.1.1 Voltage Controlled Oscillator 739
  483. 19.1.2 Divider 740
  484. 19.1.3 Phase Detector 741
  485. 19.1.4 Loop Filer 746
  486. 19.1.5 The PLL in Lock 747
  487. 19.2 Linearized Small-Signal Analysis 748
  488. 19.2.1 Second-Order PLL Model 749
  489. 19.2.2 Limitations of the Second-Order Small-Signal Model 751
  490. 19.2.3 PLL Design Example 754
  491. 19.3 Jitter and Phase Noise 756
  492. 19.3.1 Period Jitter 760
  493. 19.3.2 P-Cycle Jitter 761
  494. 19.3.3 Adjacent Period Jitter 761
  495. 19.3.4 Other Spectral Representations of Jitter 762
  496. 19.3.5 Probability Density Function of Jitter 764
  497. 19.4 Electronic Oscillators 765
  498. 19.4.1 Ring Oscillators 766
  499. 19.4.2 LC Oscillators 771
  500. 19.4.3 Phase Noise of Oscillators 772
  501. 19.5 Jitter and Phase Noise in PLLS 777
  502. 19.5.1 Input Phase Noise and Divider Phase Noise 777
  503. 19.5.2 VCO Phase Noise 778
  504. 19.5.3 Loop Filter Noise 779
  505. 19.6 Key Points 781
  506. 19.7 References 782
  507. 19.8 Problems 782
  508. INDEX 787
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八云  士官⑥  发表于 2018-12-6 00:55:12  | 显示全部楼层

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おじさん  士官⑥  发表于 2015-12-22 09:57:39  | 显示全部楼层
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ljfa  中尉  发表于 2013-6-19 07:42:21  | 显示全部楼层
谢谢               
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太阳の息子  少尉  发表于 2012-3-15 09:15:07  | 显示全部楼层
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太阳の息子  少尉  发表于 2012-3-15 09:17:29  | 显示全部楼层
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psf135  元帅  发表于 2012-3-15 09:22:40  | 显示全部楼层
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daverong  中尉  发表于 2012-3-15 09:23:37  | 显示全部楼层
Analog.Integrated.Circuit.Design.Martin.Johns.Martin,.Carusone.2ed
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zhujb1999  少校  发表于 2012-3-15 09:58:34  | 显示全部楼层
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yanghaoran1987  士官⑥  发表于 2012-3-15 10:35:23  | 显示全部楼层
感谢分享
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你好啊  士官⑥  发表于 2012-3-15 12:35:34  | 显示全部楼层
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陈豪俊  中校  发表于 2012-3-15 12:40:25  | 显示全部楼层
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bandwidth  超级版主  发表于 2012-3-15 12:45:33  | 显示全部楼层
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